EFFICIENTLY MULTI-PROGRAMMING A SINGLE PROCESSOR
B. H. Venter
Department of Computer Science, University of Port Elizabeth
P O Box 1600, Port Elizabeth, 6000 South Africa
e-mail: csabhv@upe.ac.za (now hermanv@microsoft.com)

SUMMARYA mechanism for efficiently multi-programming a single processor is explained in detail, with specific references to an implementation on the Motorola 680XX-architecture. Design alternatives are discussed and the chosen design is justified in terms of the assumptions made and requirements imposed. Potential pitfalls are highlighted and problems with the 680XX-architecture are pointed out. The multi-programming mechanism presented in the paper differs significantly from older multi-programming mechanisms and supports a novel scheduling technique for real-time processes.

Keywords operating system, process, real-time, scheduler, Motorola 680XX, computer architecture

• INTRODUCTION
• ASSUMPTIONS AND REQUIREMENTS
• PROCESS SCHEDULING
• SCHEDULING THE SCHEDULER
• AN OVERVIEW OF THE MECHANISM
• TIME-OUTS
• A REFINEMENT TO REDUCE THE COST OF A CONTEXT SWITCH
• TRAPS, PROBLEMS, AND CRITICISMS
• CONCLUSION
• References